This invention was principally motivated in addressing problems and improvements in dynamic random access memory (DRAM). As DRAM increases in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. Yet as feature size continues to become smaller and smaller, development of improved materials for cell dielectrics, as well as the cell structure, is important.
Conventional stacked capacitor DRAM arrays utilize either a Capacitor Over Bit line (COB) or a Capacitor Under Bit line (CUB) construction. With a Capacitor Over Bit line construction, the bit line is provided in close vertical proximity to the bit line contact of the memory cell field effect transistor (FET), with the cell capacitors being formed over the top of the word line and bit line. With a Capacitor Under Bit line construction, a deep vertical bit line contact is made through a thick insulating layer to the source/drain region of the cell FET access transistor, with the capacitor construction being provided over the word line and under the bit line.
The present invention relates to a method of reducing electrical shorts between the bit contact and the capacitor cell plate in a Capacitor Under Bit line cell.